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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMSDSFR_EL1, Sampling Data Source Filter Register</h1><p>The PMSDSFR_EL1 characteristics are:</p><h2>Purpose</h2>
        <p>Controls sample filtering by Data Source.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_SPE_FDS is implemented. Otherwise, direct accesses to PMSDSFR_EL1 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>PMSDSFR_EL1 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S63</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S62</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S61</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S60</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S59</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S58</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S57</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S56</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S55</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S54</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S53</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S52</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S51</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S50</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S49</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S48</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S47</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S46</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S45</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S44</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S43</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S42</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S41</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S40</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S39</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S38</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S37</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S36</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S35</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S34</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S33</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S32</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-63_0-1">S0</a></td></tr></tbody></table><h4 id="fieldset_0-63_0-1">S&lt;m&gt;, bit [m], for m = 63 to 0<span class="condition"><br/>When filtering on Data Source &lt;m&gt; is supported:
                        </span></h4><div class="field">
      <p>S[&lt;m&gt;] is the Data Source filter for <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> Data Source &lt;m&gt;.</p>
    <table class="valuetable"><tr><th>S&lt;m&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>If <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FDS is 1, do not record load operations that have bits [5:0] of the Data Source packet set to &lt;m&gt;.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Load operations with Data Source &lt;m&gt; are unaffected by <a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>.FDS.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-63_0-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, RAZ/WI.</p>
    </div><div class="access_mechanisms"><h2>Accessing PMSDSFR_EL1</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, PMSDSFR_EL1</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1001</td><td>0b1010</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HaveEL(EL3) &amp;&amp; SCR_EL3.FGTEn2 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HDFGRTR2_EL2.nPMSDSFR_EL1 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2.TPMS == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        X[t, 64] = NVMem[0x858];
    else
        X[t, 64] = PMSDSFR_EL1;
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        X[t, 64] = PMSDSFR_EL1;
elsif PSTATE.EL == EL3 then
    X[t, 64] = PMSDSFR_EL1;
                </p><h4 class="assembler">MSR PMSDSFR_EL1, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b000</td><td>0b1001</td><td>0b1010</td><td>0b100</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HaveEL(EL3) &amp;&amp; SCR_EL3.FGTEn2 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT2) &amp;&amp; HDFGWTR2_EL2.nPMSDSFR_EL1 == '0' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; MDCR_EL2.TPMS == '1' then
        AArch64.SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif EL2Enabled() &amp;&amp; HCR_EL2.&lt;NV2,NV&gt; == '11' then
        NVMem[0x858] = X[t, 64];
    else
        PMSDSFR_EL1 = X[t, 64];
elsif PSTATE.EL == EL2 then
    if Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        UNDEFINED;
    elsif Halted() &amp;&amp; HaveEL(EL3) &amp;&amp; EDSCR.SDD == '1' &amp;&amp; boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        UNDEFINED;
    elsif HaveEL(EL3) &amp;&amp; (MDCR_EL3.NSPB[0] == '0' || MDCR_EL3.NSPB[1] != SCR_EL3.NS || (IsFeatureImplemented(FEAT_RME) &amp;&amp; MDCR_EL3.NSPBE != SCR_EL3.NSE)) then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    elsif HaveEL(EL3) &amp;&amp; MDCR_EL3.EnPMS3 == '0' then
        if Halted() &amp;&amp; EDSCR.SDD == '1' then
            UNDEFINED;
        else
            AArch64.SystemAccessTrap(EL3, 0x18);
    else
        PMSDSFR_EL1 = X[t, 64];
elsif PSTATE.EL == EL3 then
    PMSDSFR_EL1 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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